1
MHT CET (PCB) 2025 9th April Evening Shift
MCQ (Single Correct Answer)
+1
-0

The output Y of a given logic circuit is (For inputs $\mathrm{A}, \mathrm{B}$ and C )

MHT CET (PCB) 2025 9th April Evening Shift Physics - Semiconductor Devices and Logic Gates Question 1 English
A

$\quad \mathrm{Y}=\overline{\mathrm{A}} \cdot(\overline{\mathrm{B}+\mathrm{C}})$

B

$\mathrm{Y}=(\overline{\mathrm{A} \cdot \mathrm{B}})+(\overline{\mathrm{B} \cdot \mathrm{C}})$

C

$ \mathrm{Y}=(\overline{\mathrm{A}+\mathrm{B}}) \cdot(\overline{\mathrm{B}+\mathrm{C}})$

D

$Y=(A+B) \cdot C$

2
MHT CET (PCB) 2025 9th April Morning Shift
MCQ (Single Correct Answer)
+1
-0

When forward bias is applied to a p-n junction, then the potential barrier and the width of the depletion region respectively.

A

increases, increases.

B

decreases, increases.

C

increases, decreases.

D

decreases, decreases.

3
MHT CET (PCB) 2025 9th April Morning Shift
MCQ (Single Correct Answer)
+1
-0

In common emitter configuration, $\beta, \mathrm{R}_{\mathrm{L}}$ and r are the a.c. current gain, load resistance and the input resistance of a transistor respectively. The voltage and power gain respectively are

A

$\beta \frac{r}{R_L}, \beta^2 \frac{r}{R_L}$

B

$\beta \frac{\mathrm{r}}{\mathrm{R}_{\mathrm{L}}}, \beta\left(\frac{\mathrm{r}}{\mathrm{R}_{\mathrm{L}}}\right)^2$

C

$\beta \frac{R_L}{r}, \beta^2 \frac{R_L}{r}$

D

$\beta \frac{R_L}{r}, \beta\left(\frac{R_L}{r}\right)^2$

4
MHT CET (PCB) 2025 9th April Morning Shift
MCQ (Single Correct Answer)
+1
-0

The order of (a) transformer (b) diode rectifier (c) filter (d) voltage regulator in a block diagram of simple rectifier circuit is as

(a) b, d, c, a

(b) a, c, d, b

(c) a, b, c, d

(d) d, c, a, b

A

d

B

a

C

c

D

b

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