1
GATE EE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
In an $$8085$$ microprocessor, the following program is executed GATE EE 2014 Set 2 Digital Electronics - Microprocessor Question 3 English

At the end of program, register $$A$$ contains

A
$$60H$$
B
$$30H$$
C
$$06H$$
D
$$03H$$
2
GATE EE 2014 Set 1
MCQ (Single Correct Answer)
+2
-0.6
An output device is interfaced with $$8$$ bit microprocessor $$8085$$$$A.$$ The interfacing circuit is shown in figure GATE EE 2014 Set 1 Digital Electronics - Microprocessor Question 4 English

The interfacing circuit makes use of $$3$$ line to $$8$$ line decoder having $$3$$ enable lines $${E_1}\,\,\overline E {}_2,$$ $$\,\overline E {}_3$$. The address of the device is

A
$${50_H}$$
B
$${5000_H}$$
C
$${A0_H}$$
D
$${A000_H}$$
3
GATE EE 2011
MCQ (Single Correct Answer)
+2
-0.6
A portion of the main program to call a subroutine $$SUB$$ in an $$8085$$ environment is given below:
$$\eqalign{ & LXI\,\,\,\,\,\,\,\,\,\,\,\,\,D\,\,\,DISP \cr & LP\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,CALL\,\,\,SUB \cr} $$

It is desired that control be returned to $$LP+DISP+3$$ when the $$RET$$ instruction is executed in the subroutine. The set of instructions that precede the $$RET$$ instruction in the subroutine are

A
$$\eqalign{ & POP\,\,\,D \cr & DAD\,\,\,H \cr & PUSH\,\,\,D \cr} $$
B
$$\eqalign{ & POP\,\,\,H \cr & DAD\,\,\,D \cr & INX\,\,\,H \cr & INX\,\,\,H \cr & INX\,\,\,H \cr & PUSH\,\,\,H \cr} $$
C
$$\eqalign{ & POP\,\,\,H \cr & DAD\,\,\,D \cr & PUSH\,\,\,H \cr} $$
D
$$\eqalign{ & XTHL \cr & INX\,\,\,D \cr & INX\,\,\,D \cr & INX\,\,\,D \cr & XTHL \cr} $$
4
GATE EE 2010
MCQ (Single Correct Answer)
+2
-0.6
When a $$''CALL$$ $$addr'$$ instruction is executed, the $$CPU$$ carries out the following sequential operations internally.

Note:
$$(R)$$ means content of register $$R$$
$$\left( {\left( R \right)} \right)$$ means content of memory locating pointed by $$R$$
$$PC$$ means Program Counter
$$SP$$ means Stack Pointer

A
$$\eqalign{ & \left( {SP} \right)\,\,\,\,\,\,\,incremented \cr & \left( {PC} \right)\,\,\,\,\,\, \leftarrow \left( {Addr} \right) \cr & \left( {\left( {SP} \right)} \right) \leftarrow \left( {PC} \right) \cr} $$
B
$$\eqalign{ & \left( {PC} \right)\,\,\,\,\,\, \leftarrow \left( {Addr} \right) \cr & \left( {\left( {SP} \right)} \right) \leftarrow \left( {PC} \right) \cr & \left( {SP} \right)\,\,\,\,\,\,\,incremented \cr} $$
C
$$\eqalign{ & \left( {PC} \right)\,\,\,\,\,\, \leftarrow \left( {Addr} \right) \cr & \left( {SP} \right)\,\,\,\,\,\,\,incremented \cr & \left( {\left( {SP} \right)} \right) \leftarrow \left( {PC} \right) \cr} $$
D
$$\eqalign{ & \left( {\left( {SP} \right)} \right) \leftarrow \left( {PC} \right) \cr & \left( {SP} \right)\,\,\,\,\,\,\,incremented \cr & \left( {PC} \right)\,\,\,\,\,\, \leftarrow \left( {Addr} \right) \cr} $$
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