In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data D_in using clock CK. The XOR gate outputs 3.3 volts for logic HIGH and 0 volts for logic LOW levels. The data bit and clock periods are equal and the value of $${{\Delta T} \over {{T_{CK}}}}$$ = 0.15, where the parameters $$\Delta T$$ and T_CK are shown in the figure. Assume that the Flip-Flop and the XOR gate are ideal.

If the probability of input data bit (D_in) transition in each clock period is 0.3, the average value (in volts, accurate to two decimal places) of the voltage at node X, is _______.

The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input 'In' and an output 'Out'. The initial state of the FSM is S₀.

If the input sequence is 10101101001101, starting with the left-most bit, then the number of times 'Out' will be 1 is __________.

A 4-bit shift register circuit configured for right-shift operation is $${D_{in}}\, \to \,A,\,A\, \to B,\,B \to C,\,C \to D,$$ is shown. If the present state of the shift register is ABCD = 1101, the number of clock cycles required to reach the state ABCD = 1111 is

A finite state machine (FSM) is implemented using the D flip-flops A and B and logic gates, as shown in the figure below. The four possible states of the FSM are Q_A Q_B = 00, 01, 10, and 11.

Assume that X_IN is held at a logic level throughout the operation of the FSM. When the FSM is initialized to the state Q_A Q_B = 100 and clocked, after a few clock cycles, it starts cycling through