1
GATE CSE 2018
MCQ (Single Correct Answer)
+2
-0.6
Consider the following processor design characteristics.

$$\,\,\,\,\,\,\,{\rm I}.\,\,\,\,\,$$ Register-to-register arithmetic operations only
$$\,\,\,\,\,{\rm I}{\rm I}.\,\,\,\,\,$$ Fixed-length instruction format
$$\,\,\,{\rm I}{\rm I}{\rm I}.\,\,\,\,\,$$ Hardwired control unit

Which of the characteristics above are used in the design of a $$RISC$$ processor?

A
$${\rm I}$$ and $${\rm II}$$ only
B
$${\rm I}$$$${\rm I}$$ and $${\rm III}$$ only
C
$${\rm I}$$ and $${\rm III}$$ only
D
$${\rm I},$$ $${\rm II}$$ and $${\rm III}$$ only
2
GATE CSE 2016 Set 1
Numerical
+2
-0
The size of the data count register of a $$DMA$$ controller is $$16$$ bits. The processor needs to transfer a file of $$29,154$$ kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the $$DMA$$ controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is ___________.
Your input ____
3
GATE CSE 2013
MCQ (Single Correct Answer)
+2
-0.6
Consider the following sequence of micro-operations
$$\eqalign{ & \,\,\,\,\,\,\,\,\,\,\,\,\,MBR\,\,\,\,\,\,\, \leftarrow PC \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,MAR\,\,\,\,\,\,\, \leftarrow X \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,PC\,\,\,\,\,\,\,\,\,\,\,\, \leftarrow Y \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,Memory\, \leftarrow MBR \cr} $$

Which one of the following is a possible operation performed by this sequence?

A
Instruction fetch
B
Operand fetch
C
Conditional branch
D
Initiation of interrupt service
4
GATE CSE 2005
MCQ (Single Correct Answer)
+2
-0.6
Consider the following data path of a $$CPU$$ GATE CSE 2005 Computer Organization - Alu Data Path and Control Unit Question 4 English

The, $$ALU$$, the bus and all the registers in the data path are of identical size. All operations including incrementation of the $$PC$$ and the $$GPRs$$ are to be carried out in the $$ALU.$$ Two clock cycle are needed for memory read operation-the first one for loading address in the $$MAR$$ and the next one for loading data from the memory but into the $$MDR.$$

The instruction $$''add$$ $$R0$$, $$R1''$$ has the register transfer interpretation $$R0 < = R0 + R1.$$ The minimum number of cycles needed for execution cycle of this instruction is

A
$$2$$
B
$$3$$
C
$$4$$
D
$$5$$
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